DS1672S-3/T&R【PDF 3/15 页】IC TIMEKEEPER 3V 32-BIT 8-SOIC

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Sheet目录1994

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DS1672

11 of 15

Figure 5. Programmable Trickle Charger

2C Serial Data Bus

The DS1672 supports a bidirectional I

2C bus and data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls

the message is called a master. The devices that are controlled by the master are slaves. The bus must be

controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates

the START and STOP conditions. The DS1672 operates as a slave on the I

2C bus. Connections to the bus

are made via the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode

(100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1672

operates in both modes.

The following bus protocol has been defined (Figure 6):

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line from high to low, while the clock line is

high, defines a START condition.

Stop data transfer: A change in the state of the data line from low to high, while the clock line is

high, defines a STOP condition.

1 OF 16 SELECT

NOTE: ONLY 1010 ENABLES

1 OF 2

SELECT

1 OF 3

SELECT

TCS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

250

TRICKLE CHARGE REGISTER

TCS = TRICKLE CHARGER SELECT

DS = DIODE SELECT

RS = RESISTOR SELECT

VCC

VBACKUP

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